| 摘要 |
PURPOSE:To eliminate the phase difference between both right/left channels in a stereo signal subject to time division multiplex by activating the 1st gate and the 2nd gate at the same time and outputting as a signal of plural channels of the same phase. CONSTITUTION:An output terminal of an AND gate 1 is led out to a shift clock pulse output terminal 18, and an output terminal of an AND gate 16 is led to a gate clock pulse output terminal 19. A shift clock pulse (b) is fed to a shift register 7 from the terminal 18 and a gate clock pulse (c) is delayed by a delay circuit 13 from the output terminal 19 and the result is fed to the 1st gate 8 ad the 2nd gate 9 as a gate clock pulse c'. Further, the delay circuit 13 plays a role of awaiting the inputted gate clock pulse (c) until the signal inputted to each gate reaches a stable potential and impressing the result as the gate clock pulse c'. |
