| 摘要 |
A multi-stage packet switching network (100) includes a plurality of packet switching nodes (110) each included in one stage of a sequence of stages (101, 102, 103) of the network. Each node (101-1-x) of a stage (101) is connected to a stage bus (220-1) that indicates to the node "how manieth" stage in the sequence of stages it is a part of, i.e., where in the sequence of stages that node appears. Each node includes circuitry (450) that responds to the information carried by the associated stage bus to select "that manieth" most significant bit (504) of the destination field (502) of a received packet (500) as the bit on the basis of whose value the packet is routed at the node. On a circuit pack (200) that includes nodes of a plurality of stages, the first stage bus is connected to a register (250) whose contents are the number of the first stage of the pack in the sequence of stages. Adders (210) interconnect the stage buses of sequential stages and act to increment by one the value carried by each sequential stages' stage bus. |
