| 摘要 |
Arrangement for variably delaying analog NF signals. The NF signal is sampled with a predetermined clock cycle, is digitised in an analog/digital converter and is written into a read-write memory. The addresses for the memory locations of the read-write memory are produced by a chain of counters whose final counter state can be selected. The counters run cyclically at the predetermined clock cycle between the zero position and the selectable final counter state. A signal value which is written into a memory location of the read-write memory is read out after a counting cycle when the chain of counters produces the corresponding address, and is passed to a digital/analog converter before a new signal value is written into the memory location which has become free, within the same clock-cycle period.
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