FREQUENCY DIVIDER CIRCUIT SYSTEM

摘要

A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip-flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flip-flops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger of a malfunction in the system.