| 摘要 |
A logic signal level converter circuit arrangement for connecting the output of a saturated type logic circuit to the input of an unsaturated logic circuit, in which at least one input signal terminal is connected via a respective rectifying junction to a common point that is connected via a resistor to a first supply voltage terminal, the common point being connected via a further rectifying junction to the base of an emitter-follower transistor whose collector is connected to said first supply voltage terminal via a resistor, the emitter of said emitter follower transistor being connected to the base and collector of a multi-emitter transistor which has one emitter connected to a point of fixed potential and a second emitter connected to a second supply voltage terminal of polarity opposite to that of said first supply terminal via a voltage divider consisting of two resistors connected in series and having their junction connected to an output terminal.
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