| 摘要 |
Reversible ternary counter utilizing standard flip-flops and logic gates to provide a low cost counter having an easily decoded output. Means is included for generating a carry pulse whenever the counter overflows in either counting direction and for generating a rounding pulse if the counter is reset while in its high output state. A plurality of stages incorporating the invention can be cascaded to provide a counter having 3N output states, where N is the number of stages cascaded.
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