Programmable data path width in a programmable unit having plural levels of subinstructions sets.

摘要

A processor is disclosed having two levels of subinstructions, each stored in its own memory with the lower level memory containing only a limited set of such lower level instructions with the rest of the lower level instructions that are desired to be used being supplied by the code stream from the upper level memory. The processor data bus is selectable as either a 16 bit or 32 bit wide bus under programmable control.