发明名称 PSEUDO FAULT GENERATING SYSTEM
摘要 PURPOSE:To generate a pseudo fault during execution of an instruction without providing a circuit for pseudo fault in a CPU by changing a stop address value in a diagnostic program, a scan address of a pseudo fault register and a set value of the said register. CONSTITUTION:A maintenance exclusive instruction included in a diagnostic program is stored in an instruction register 12 of a CPU 10 of a system, the instruction is decoded by a decoder 13 to designate the execution stop of the program at an operation section 11, the diagnostic mode is set to cause interruption to a service processor 40. A fault detection register 17 to which a specific designated value representing the pseudo fault is substituted is included in the operation section 11 and a specific address stopping the execution of the program is stored in the stop address register 15. Then an address stop device 16 provided between the register 15 and the operation section 11 stops the execution of the address coincident with the content of the register 15 during execution of the program and a shift register control section 14 between the registers 15 and 17 controls the register 17.
申请公布号 JPS6167146(A) 申请公布日期 1986.04.07
申请号 JP19840187487 申请日期 1984.09.07
申请人 NEC CORP 发明人 AOKI HIROMICHI
分类号 G06F11/22;G06F11/263 主分类号 G06F11/22
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