| 摘要 |
PURPOSE:To obtain an output with less time delay against data change by applying filtering at each bit. CONSTITUTION:A coincident logic is outputted at a bit where logic of s(tn) and s(tn-d) are coincident and the logic obtained by the preceding sampling is outputted in a bit where no logic is coincident. That is, in case of [s(tn)='1', s(tn-d)='1'] and [s(tn)='0', s(tn-d)='0'], an output of an exclusive OR circuit 2 goes to logical 0 and an AND circuit 3 blocks the pass of s(tn-1), then s(tn)[=s(tn-d)] is outputted as p(tn). Further, in case of [s(tn='1', s(tn-d)='0'] and [s(tn)='0', s(tn-d)='1'], the output of the exclusive OR circuit 2 is logical 1 and the output of the AND circuit 1 is logical 0, then p(tn-1) is outputted as the p(tn). |
