Modular multi-channel clock synchronizer.

摘要

A modular synchronizer for use in synchronizing individual signal processors in a multiprocessor system is disclosed. Each synchronizer has a counter for counting its assiciated processor's clock pulses and, upon reaching a selected count, providing a counter frame output signal at an output thereof for use by each of the other synchronizers in the system. Each synchronizer has a voter responsive to counter output signals from each of the other synchronizers, and from itself as well, at input ports thereof. Each synchronizer's voter provides a frame sync (macro sync) pulse in each counter frame after receiving a selected number of counter frame output signals from any of the synchronizers in the system. Each synchronizer's voted frame sync pulse is provided at an output port of the synchronizer and may be utilized, depending on the application, for routing back into the synchronizer at a frame sync input port for resetting the synchronizer at a frame sync input port for resetting the synchronizer's counter, or for routing to one or more (slave) synchronizers for the same purpose. Each synchronizer's voter includes a rising edge voter that arms a falling edge voter only during a selected portion of the expected counter frame period (voting window). The synchronizer voter architecture can include clocked latches or not. The synchronizer may include fast and slow clock detectors. The synchronizer interfaces with its associated processor and includes disable circuitry for permitting the CPU to disable nonfunctional frame sync signals.