| 摘要 |
<p>The circuit comprises a first pair of n and p-channel MOSFETS, T1 and T2, whose gates are connected to form the trigger input, whose sources are commoned at node B and whose drains are respectively connected to the positive supply rail (3) and the ground rail (4). Node B is connected to the input of a standard CMOS inverter comprising second p and n-channel MOSFETS T3 and T4. A third p-channel MOSFET T5 has its gate connected to the output of the inverter, its source connected to the positive supply rail and its drain connected to node B. A third n-channel MOSFET T6 also has its gate connected to the output of the inverter, its drain connected to node B, and its source connected to the ground rail.</p><p>T5 and T6 act as pull-up and pull-down MOSFETS for the node B to ensure that T4 and T3 are respectively turned hard on when the input at A is high or low.</p><p>The threshold for response to a high going signal at input A is determined by the ratio of the sizes of T6 and T1. Similarly, the threshold for response to a low going signal is determined by the ratio of the sizes of T5 and T2.</p> |
