| 摘要 |
A processor, for providing a double line-rate video output signal comprising alternating received lines and interpolated lines, comprises three memories. As each line of incoming video signal is stored in one of the three memories, at a given clock rate the remaining two memories are read at double the write clock rate. A single averaging circuit, having inputs selectively coupled to the memories, interleaves non-interpolated time compressed lines of video obtained from one of the two memories being read with time-compressed lines of video obtained by interpolation from both of the two memories being read to provide a processed video output signal. The "write-one read-two" memory organization enables concurrent interpolation and speed-up of the video signal thereby minimizing potential clock timing problems inherent in progressive scan systems of the type where interpolation is provided separately either before or after video speed-up.
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