| 摘要 |
A circuit arrangement for compensation of the direct current disturbance component in the demodulation of frequency modulated binary data signals is described. The discriminator output is coupled to a first input of two difference amplifiers. A limiter at the output of one of the difference amplifiers produces a correct d.c. signal, which signal is coupled to a second input of the other difference amplifier. A timing element couples the output of said other amplifier to a second input of said one difference amplifier.
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