发明名称 TIME DIVISION MULTIPLEX CONVERTING INTEGRATED CIRCUIT
摘要 PURPOSE:To miniaturize the circuit constitution by using an external clock signal having the same frequency as a frequency-divided clock signal but different in phase to control the phase of the frequency-divided clock signal and the external clock signal to a desired value. CONSTITUTION:When a data terminal device is operated by a clock of a time division conversion LSI30 and the data terminal device transmits a transmission data by using a unique clock where the frequency is coincident but the phase is different, the clock incoming from the data terminal device is used as an external clock and a phase control circuit 38 controls a frequency division circuit 37. In specifying the frequency-divided clock, especially the phase of the clock to a register 40 and the external clock, the data processed by the data terminal device is fetched to the inside of the LSI30 without being mistaken as the internal clock of the LSI30 even when no buffer memory is used.
申请公布号 JPS6163127(A) 申请公布日期 1986.04.01
申请号 JP19840185255 申请日期 1984.09.04
申请人 FUJITSU LTD 发明人 IGUCHI KAZUO;YANO KENJIRO
分类号 H04J3/06;H04L7/033;H04L7/04 主分类号 H04J3/06
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