SEMICONDUCTOR DEVICE

摘要

PURPOSE:To attain ease of high-speed operation test by inputting a signal inverting an output signal of an FF of each bit of a shift register to each FF. CONSTITUTION:A set comprising an FF1 and an input signal control logical circuit 2 is connected by a required bit number (n) and inputs P1-Pn of each bit are fed to inputs D1-Dn of the FF1. An inverting signal of outputs Q1-Qn of the FF is connected to the inputs P1-Pn of each bit through a wire 3 possible for fusing. As a result, a 1/2 frequency-divider using FFs is constituted with respect to each bit and a frequency being a half the frequency of a timing signal CLK is obtained respectively at the outputs Q1-Qn. Thus, the FF operation test is conducted as to each bit to forecast the shift register.