| 摘要 |
PURPOSE:To avoid performance deterioration despite an input terminal not in use by a method wherein, in a multiple input CMOS gate array, drain and source of a P or N type transistor are shortcircuited after idle pin processing at high or low level. CONSTITUTION:When a CMOS three input NAND circuit is utilized making use of two terminals A, B only with terminal C not in use, proper measures are taken as mentioned below i.e. any input into the terminal C is connected to a power supply VDD through a through hole 2 to be held at high level however the falling down time is delayed in terms of performance due to the impedance for three transistors exerted for utilization as two input NAND circuit since N type transistors N1-N3 are utilized for discharging load capacity CL if the state is as it is. Therefore a proper circuit for two input NAND may be made utilizing an aluminum wiring 1 to shortcircuit source and drain of a transistor N1. |
