发明名称 VECTOR PROCESSOR
摘要 PURPOSE:To extend the expression range of numbers b making the exponential part data width of internal operation data in a macro operation such as the operation of the total sum, the inner product, or the like wider than that of input data. CONSTITUTION:When the operation of the total sum is started, scalar data is set to an input register 53 through a data converting circuit 50 and a selector 52, and vector data is set to an input register 54 trough a data converting circuit 51, and they are added an adder 11-1-1. The addition result is set to the input register 53 trough a output register 55 and the selector 52. Simultaneously, vector data is set to the input register 54 and is added o the addition result, and te result is set to the input register 53. Data converting circuits 50 and 51 perform processings to increase the number of bits of the exponential part for the purpose of extending the expression range of the floating-point number. Finally, the total sm of vector data is set to the output register 55.
申请公布号 JPS6162973(A) 申请公布日期 1986.03.31
申请号 JP19840184620 申请日期 1984.09.05
申请人 HITACHI LTD 发明人 OMODA KOICHIRO
分类号 G06F7/00;G06F17/16 主分类号 G06F7/00
代理机构 代理人
主权项
地址