| 摘要 |
PURPOSE:To attain correct synchronization of parity bit location by using the 2nd frequency division signal to shift a 1/2 frequency division signal of an mBIP code signal and detecting the keeping state of a parity from a shift position output signal to result in controlling the 2nd frequency dividing means. CONSTITUTION:An AND circuit 3 ANDs an mBIP code signal at a terminal 1 and a clock signal at a terminal 2 and an output signal of the circuit 3 is subjected to 1/2 frequency division by a 1/2 frequency division circuit 5. An output signal of the circuit 5 is inputted sequentially to FF1, FF2 by using a clock signal subject to 1/(m+1) frequency division by a 1/(m+1) frequency division circuit 4. When a parity bit is not synchronized, when the parity is an even parity, an output signal of an exclusive OR circuit 6 goes to '1', and when the parity is an odd parity, an output signal of the circuit 6 goes to '0'. A protection circuit 7 responding to the output signal of the circuit 6 shifts one after another the output signal of the circuit 4 and attains the synchronization for parity bit. |
