发明名称 FAULT DIAGNOSIS SYSTEM FOR MICROPROGRAM CONTROLLER
摘要 PURPOSE:To reduce the hardware quantity compared with a case where a micromemory is held by providing an address holding means which holds an address of a control memory when a fault detecting circuit detects a fault. CONSTITUTION:An error display flip-flop is set in response to the parity error signal given from a parity check circuit. Then the supply of clocks is stopped. Address registers AR1-AR4 holds addresses AD1-AD4 respectively, and a microinstruction register MIR holds a microinstruction MI3 corresponding to an address AD3. An operator operates a service processor SVP to read out the address AD1 and gives an access to a control memory CS to read out a microinstruction MI1 to the register MIR. Thus the address of a control memory is held when a fault is detected for read-out the microinstruction. This can reduce the hardware quantity.
申请公布号 JPS6160143(A) 申请公布日期 1986.03.27
申请号 JP19840182118 申请日期 1984.08.31
申请人 NEC CORP 发明人 ISHIKAWA AKIHIKO
分类号 G06F9/22;G06F11/07;G06F11/22 主分类号 G06F9/22
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