| 摘要 |
PURPOSE:To attain high speed operation with less hardware and to make the device suitable for LSI by utilizing the shift operation of a data attended with operation, inputting sequentially the data divided in the unit of shift and generat ing a remainder by repetitive operation. CONSTITUTION:Low-order 2 bits b1, b0 of a multiplier of a data register 3 are inputted to a multiplier remainder generating circuit 37 in the same timing as that of a multiplier decode and set to a latch 38, which is set initially to 0. As a result, a 4-bit data remainder generating circuit 17 has a remainder of low-order 2-bit. In the next cycle, the register 3 is shifted by 2-bit right, the low-order 2-bit after shift of the multiplier is inputted to the circuit 37, the said 2-bit input and the remainder of the preceding cycle is fed back to the latch 38, resulting that a 4-bit remainder is generated in the circuit 17. The multiplier remainder is generated finally at the output of the circuit 17 by executing repetitively the operation in matching with the multiplication. |
