| 摘要 |
PURPOSE:To prevent a floating potential from leaking to a substrate even if a pinhole is produced in an SiO2 layer directly under the first wiring layer by interposing an impurity region of reverse conductive type to the substrate between the SiO2 layer and the substrate. CONSTITUTION:3 wirings layers 3, 5, 7 are formed. In case of a complementary MOS element, a p-type well 12 is formed in an n-channel element forming region of an n type Si substrate 11, and further the source drain regions 13, 14 of the n-channel element and the source and drain regions 15, 16 of a p-channel element are formed. When the channel stop regions 17A, 17B, 17C of the n- channel element are then formed, an impurity region 17D of reverse conductive type (p-type) to the substrate 11 is formed simultaneously at the positions of opening twice windows of the layers 4, 6 on the first A1 wiring layer 3. When the channel stop regions 18A, 18B, 18C of the p-channel element are formed, an impurity region 18D of reverse conductive type (n-type) to the p-well 12 of the substrate 11 is formed at the positions of opening twice windows of the layers 4, 6 on the first A1 wiring layer 3. |
