发明名称 SWITCHED CAPACITOR INTEGRATOR
摘要 PURPOSE:To obtain an integrated output to the absolute value of an input signal, by selectively operating an output switch and supplying the electric charge of the input signal charging a sampling capacity to a current integrating circuit. CONSTITUTION:Analog switches A1, A2, and K2 operate in accordance with a clock phiA and an analog switch J2 operates in accordance with another clock phiB. Output switches D1 and D2 operate at the timing of the clock phiB in such a way that when a discriminated output S is positive the switch D1 operates and when negative the switch D2 operates. The electric charge of an input signal charging sampling capacities B1 and B2 at the timing of the clock phiA is simultaneously converted into a digital signal and supplied to a current integrating circuit N when either one of the output switches D1 and D2 operates at the timing of the clock phiB. Therefore, an integrated output (y) to the absolute value of the input signal (x) is obtained at an output terminal 6.
申请公布号 JPS6158310(A) 申请公布日期 1986.03.25
申请号 JP19840181047 申请日期 1984.08.30
申请人 SEIKO EPSON CORP 发明人 IIDA ATSUSHI
分类号 H03H19/00;(IPC1-7):H03H19/00 主分类号 H03H19/00
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