| 摘要 |
PURPOSE:To take an error-free test in a short time without increasing the number of IC terminals by controlling the supply and stop of a clock to a counter and the generation of a test clock by using an existent test terminal. CONSTITUTION:When test commands are supplied by using the address terminal and write terminal of a timepiece IC, the count clock stop signal outputted by a decoder 104 is inverted to L to close an AND gate 103, and the supply of the clock from a frequency dividing circuit 102 to counter circuits 106 and 107 is stopped. At the same time, a test pulse control signal is applied from the decoder 104 and a test pulse generating circuit 105 outputs and supplies a test high-frequency clock to the counters 106 and 107 every time a read signal is applied from a read terminal. The stop of the clock from the circuit 102 is reset similarly after the test, and the error-free test is taken in a short time without any increase in the number of external terminal nor step-out. |
