发明名称 PLL CIRCUIT
摘要 PURPOSE:To reduce the synchronism restoring time at re-input of reference frequency signal by sampling and holding an output of a LPF controlling a VCO and controlling the VCO with a sample-and-hold output when the reference frequency signal is interrupted. CONSTITUTION:When the reference frequency signal is inputted to a signal line 102, a phase comparator 1 compares the phase of an output signal of the VCO3 with that of the reference frequency signal and a signal through an LPF2 from an output signal of a comparator 1 controls the VCO3 via a switch 6. Similarly, a sample-and-hold circuit 4 samples always an output of te LPF2. When the reference frequency signal is interrupted, a reference frequency signal interruption detector 5 detects it, the detected signal controls the circuit 4 to stop sampling and the signal just before is held and the switch 6 is changed over to the position of the circuit 4, and the holding signal of the circuit 4 controls the VCO3. Thus, since a large frequency fluctuation is not caused even if the reference frequency is interrupted, the synthronism restoring time when the reference frequency is inputted again is shortened.
申请公布号 JPS6157122(A) 申请公布日期 1986.03.24
申请号 JP19840178989 申请日期 1984.08.28
申请人 NEC CORP 发明人 SUZUKI HIDEHIKO
分类号 H03L7/14 主分类号 H03L7/14
代理机构 代理人
主权项
地址