| 摘要 |
PURPOSE:To convert easily and successively the reception data into fixed signals by a decoding/bit length detecting circuit while counting down the 1st and 2nd counters, by supplying the variable length DPCM reception data to a serial/ parallel converting circuit via a parallel/serial converting circuit and setting the number of component bits and the bit length of the reception data to the 2nd and 1st counters respectively. CONSTITUTION:The reception data '01010010' (8 bits) shown by a figure (a) is supplied to a serial/parallel converting circuit S/P together with a reception strobe signal shown by a figure (c). The next reception data 'xy...' is supplied to a parallel/serial circuit P/S. While a digit ''8'' is supplied to a counter COUNT2 concurrently with the reception strobe signal. Then a decoding/bit length detecting circuit DET checks the contents of the circuit S/P since the value of a counter COUNT1 is equal to 0 from the start. It is decided that the bit length and the decoding data are equal to 1 and 0 respectively since the 1st bit is equal to ''0''. Then the bit length 1 is loaded to the COUNT1. |
