| 摘要 |
A circuit arrangement is described with a sense latch for increasing the number of dynamic FET storage cells on bit lines (BL) connected to this sense latch (SL). The storage cells proper are arranged in a semiconductor structure having a diffusion layer acting as a conductor and a multiple metal layer. The outputs of the sense latch (SL) are connected to two pairs of cross-coupled charge storge elements (BB) acting as bit line coupling transistors which are connected to extended partitioned bit line pairs (BL1, BL1', and BL2, BL2'). Each section has its own reference cells and is coupled to the sense latch (SL), the sections furthest from the sense latch are coupled through low-capacity metal lines, and charge coupling elements (BB). These metal sections of the bit lines meander over the surface of the semiconductor structure. |
