| 摘要 |
PURPOSE:To conduct a final test after assembly easily by disposing a shift register and a bonding pad, which is connected to each step of the shift register and also connected to an adjacent chip, along a side adjacent to the adjacent chip. CONSTITUTION:A scanning control signal CNT is brought to an H level, and a scanning clock LCK is inputted continuously. Consequently, AND gates G2, G5,... are opened, and an output from a pre-step FF is inputted to a post-step FF, thus extracting an inter-chip signal taken into a shift register SR from a pad 20A for a scanning-out. That is, a parallel-in and a series-out are conducted. When input-output gates for an FF are varied slightly, the series-in and the parallel- out are also enabled, a test data to a next-step LSI chip 10B is inputted to a scanning pad 20B in a shape of a series signal at that time, the test data is made to contain into each FF for a SR18 and the series-in and the parallel-out is changed over to the parallel-out, and the test data is inputted in parallel to the next-step LSI chip through bonding wires 14. Accordingly, when the SR18 is fitted, the inter-chip signal is inputted and outputted easily, and the method is extremely effective to a performance test for a chip. |
