| 摘要 |
PURPOSE:To realize a FET having small source resistance and large Schottky reverse withstanding-voltage by independently setting a distance between a source-side high concentration layer and a gate electrode and a distance between a drain-side high concentration layer and the gate electrode. CONSTITUTION:An N type GaAs operating layer 102 is formed onto a semi- insulating substrate 101, a metallic layer 1 for shaping Shottky contacts consisting of a WN layer 11 and an Au layer 21 is formed to source, drain and gate forming prearranged sections, and insulating films 2 are shaped among said each prearranged section. The WN layer 11 and the Au layer 21 are removed through etching by using a mask 3, Si<+> is implanted from the upper surface of the N type GaAs operating layer 102 exposed through the removal of the layers 11, 21, and N type GaAs high concentration layers 4s, 4d are shaped in each region of a source and a drain and activated. Accordingly, a distance lSG between the high concentration layer 4s and the gate electrode 1 is shortened and source resistance can be reduced, and a distance between the high concentration layer 4d and the gate electrode 1 is lengthened and Schottky reverse withstanding voltage between a gate and the drain can be increased. |
