| 摘要 |
In the circuit arrangement described, the normal functional sequence of an AMI coder is interrupted under control by the edges of an error set signal, in such a manner that exactly one code rule violation occurs per edge of the error set signal in the AMI-coded binary NRZ signal. Binary signals with bit rates of up to 700 Mbit/s can be processed by means of a special embodiment of the arrangement.
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