发明名称 CLOCK GENERATOR
摘要 <p>PURPOSE:To prevent abnormal oscillation of an oscillation circuit and to improve the reliability by applying a power voltage given with a delay by a power supply time constant circuit to an oscillation circuit and obtaining a clock signal at the output side. CONSTITUTION:A logical circuit section 13 includes elements such as a set logical circuit 131 and a ready synchronizing circuit 132. In applying power to the logical circuit, since the effect of the leading speed of the supply voltage due to power ON is not almost given, the application of the power supply Vcc is branched from the input side of the power supply time constant circuit 11. The circuit 13 receives a clock signal from the oscillation circuit 12 and the power voltage Vcc, executes a prescribed logical operation and a clock generator outputs a signal such as a clock signal S(CL), a reset signal S(RST) and a ready signal S(RDY) from the output side.</p>
申请公布号 JPS6155720(A) 申请公布日期 1986.03.20
申请号 JP19840176709 申请日期 1984.08.27
申请人 FUJITSU LTD 发明人 TADA YOSHIHIRO
分类号 G06F1/04 主分类号 G06F1/04
代理机构 代理人
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