| 摘要 |
The invention relates to the reduction of leakage current in a CMOS digital-to-analog converter of the type which comprises a plurality of switch-pairs (12A, 12B) in a common well (34), the individual switches of each pair being complementarily driven by switch drivers (30, 32) to "on" and "off" condition respectively to switch a corresponding terminal of a resistance network (R-2R) to one or the other of a pair of output lines in accordance with the state of an input bit, each switch having a driving gate and a back gate. Bias means is provided to develop a predetermined potential difference between the output lines and the well, with the well being more negative than the output lines, thereby to avoid bipolar leakage current. In one embodiment, the back gates of the CMOS switches (12A, 12B) are held at -200 mV with respect to the output lines, and the logic low level to the off switch also is set at -200 mV relative to the output lines. <IMAGE> |
