| 摘要 |
Semiconductor memory cell having a memory electrode (5) which defines a memory region (SP) and which is arranged, in an insulated manner on the boundary surface of a semiconductor body, and having a selection transistor which has a terminal region (8) connected to a bit line and oppositely doped to the semiconductor body. An attempt is made to store both logic states of the cell without external regeneration measures for as long as is required. This is achieved by an extraction transistor whose gate (9) covers a semiconductor region (AS) situated next to the memory region (SP) and is conductively connected to the boundary surface in the memory region, the extraction transistor having an extraction region (10) which is capacitively connected to the gate (9) of the extraction transistor and to an extraction clock voltage (VP). The field of application comprises VLSI memory applications. <IMAGE> |
