| 摘要 |
PURPOSE:To decrease the number of input terminals and to utilize effectively an input buffer by interposing exclusive OR circuits among plural counters which are connected in series, connecting output terminals of respective chip selectors to other-input sides of those circuits, and controlling address input terminals of the chip selectors and confirming the operation of a desired counter. CONSTITUTION:When a 4-bit counter 56 is tested, address input terminals 36, 37, and 38 are held at 0, 0, and 0 respectively and a clock pulse is inputted to a clock pulse input terminal 35, thereby confirming the operation of the 4-bit counter 56 with the output at an output terminal 39. Then, when a 4-bit counter 55 is tested, the address input terminals 36, 37, and 38 are set to 0, 0, and 1 and a clock pulse is inputted to the clock pulse input terminal 35, thereby confirming the operation of the 4-bit counter 55 with the output at the output terminal 39. Thus, a control circuit 31 specifies address input terminals 36-38 to confirm the operation of all 4-bit counters 48-56, one by one. |
