| 摘要 |
<p>PURPOSE:To transmit and receive transfer data correctly by sampling a transmission/reception element timing signal ST2/RT from a modem correctly regardless of whether data communication is performed at a slow or high speed. CONSTITUTION:When a flip-flop FFa is off, an AND circuit A14 performs AND operation with a sample signal A, so the sample signal A is inputted to AND circuits A111 and A112 through an OR circuit 114 to obtain functions in low speed mode, thereby generating a clock for the detection of the leading and trailing edge of the transmission/reception element timing signal ST2/RT sent out of the modem on the AND condition of the sampling signal A and clock CLK similarly to the conventional system. Then, when the flip-flop FFa is on, the output of the flip-flop FFa is inputted to AND circuits A111 and A112 through an OR circuit 114 directly, so a clock to the flip-flop FFs (b) and (e) is detected with the clock CLK of a circuit connection part 1 itself, thereby obtaining functions in high speed mode.</p> |
