| 摘要 |
PURPOSE:To reduce the wiring resistance without increasing the wiring width or the wiring width per a layer, by a method wherein another layers wirings are connected parallel between a part of wirings section of a part layer in multiple layers wirings of metallic or metallic compound. CONSTITUTION:Wirings 11a-11d are provided at the first layer, and wirings 21a-21d are provided at the second layer, and penetrating hole 31a-31g, operation layers 41a, 41b of FETs and gate electrodes 51a, 51b are provided. The wiring 21a is connected parallel with the wiring 11c of the first layer at the space from the penetrating hole 31c to 31e, and the wiring resistance at this section is reduced. In this case, the wiring 11c is placed at the space of each pattern on an IC, and there is no need to increase the area of IC tip. Accordingly, the wiring resistance is lowered and there is no need of increasing the wiring film width. |
