| 摘要 |
PURPOSE:To improve the degree of integration, and to lower parasitic capacitance between a collector and a base and base resistance by forming a device in vertical type structure, shaping a base leading-out section to the side wall of a base region and constituting the base leading-out section by a metal. CONSTITUTION:An n<+> type GaAs layer 2 and an n<-> type GaAs layer 3 (a collector) are formed onto a semi-insulating GaAs substrate 1. An SiO2 layer 6 a refractory metal layer 7 and an SiO2 layer 8 are shaped in succession. The layers 8-6 are removed from a section corresponding to an emitter-base forming region 9 and a section on a collector-electrode leading-out region 3'. A p type GaAs layer 11 (a base) is formed in the region 9 so as to be in contact with the layer 7, and an n type AlGaAs layer 12 (an emitter) and an n<+> type GaAs layer 13 are shaped onto the layer 11. The layer 8 is removed from a base-electrode forming region, and base electrode 14, an emitter electrode 15 and a collector electrode 16 are each formed into said base-electrode forming region, onto the layer 13 and into the region 3'. |
