| 摘要 |
<p>A serial-parallel shift register (2) divides the base digital signal into eight-bit data words, and passes them to a programmed memory (3). The ROM (3) converts each eight-bit base word into a corresponding ten-bit converted word. 256 (i.e. 2 power 8) of the 1024 possible ten-bit combinations are chosen to satisfy the following constraints. Firstly, the dc component in the converted signal must be zero. Then, because NRZ1 coding is used, the number of consecutive digital zeros in the converted signal must not exceed three. - In the result, there are 193 primary ten-bit combinations which satisfy the constraints. Consequently, a further 63 ten-bit combinations, for which the dc component is not zero, are used. These are secondary combinations and they have dc components of 0, -2 and +2 when they are NRZ1-coded. A shift register (4) combines the converted words from the memory to form a converted signal which is then modulated (6) to provide the NRZ1 code.</p> |
