Internal bus architecture for high-speed digital computer

摘要

An internal bus connects each of the independent bus units (14, 16,22) to the CPU (12). In each bus unit an instruction decoder decodes the bus instructions received from the CPU on the internal bus and determines if the respective bus unit is being requested. In addition, the unit determines which operation is being requested and provides the data necessary for identifying the partic. operands required for performance of the requested operation. - The internal bus has four sets of unidirectional lines. A first set is for sending data to a bus unit, a second set sends data from a bus unit to the CPU, a third set carries address data to a bus unit from the CPU and fourth set carries instructions and control data between the CPU and the bus units. These data include specification of the protocol to be followed by the CPU and by the bus unit for performing the requested operation.