| 摘要 |
<p>PURPOSE:To decrease remarkably a clock frequency by dividing a video signal driving circuits into plural circuits. CONSTITUTION:An active matrix array 2, a gate line driving circuit 3 for driving a gate line, and drain line driving circuits 4, 5 and 6 are formed in an active matrix liquid crystal display device 1. In this state, the driving circuit 3 scans successively the gate line in the vertical direction by synchronizing with a C-clock signal, and a D-clock signal and Vv1, Vv2 and Vv3 being video signals are applied to the driving circuits 4, 5, respectively. The driving circuits 4, 5 and 6 drive a drain line of 1/3 of one picture, respectively, therefore, the frequency of the D-clock signal is about 1/3 better than the case when one scanning line is scanned by only one shift register. Accordingly, the clock frequency can be decreased remarkably.</p> |
