| 摘要 |
<p>PURPOSE:To obtain stability by discharging a capacitor with a stop instruction and stopping oscillation when the capacitor becomes a prescribed low potential and charging the capacitor when oscillation is started and supplying a system clock when it becomes a prescribed high potential. CONSTITUTION:When a flip-flop (FF) 4 is set to ''1'' by the stop instruction, an NMOS7 is turned on, and discharging of a capacitor 5 is started. Since a gate 9 has a low threshold and a gate 8 has a high threshold value, the output of the gate 8 is first set to ''1'' to close a selecting gate 3, and the supply of clocks to the system is stopped, and thereafter, the output of the gate 9 is set to ''1'' to stop oscillation of an oscillating circuit 1. When the FF4 is reset, a PMOS6 is turned on simultaneously with the start of oscillation of the oscillating circuit 1, and the capacitor 5 is charged. When the potential reaches the threshold value of the gate 8, the output of the gate 8 is set to ''0'' to open the selecting gate 3, and clocks are supplied to the system.</p> |
