| 摘要 |
<p>PURPOSE:To access to ROM, RAM and I/O freely from CPU connected from the external part through a two-way buffer by separating CPU with a bus separating switch. CONSTITUTION:A bus control part 15 is operated by a request signal from CPU21, a bus separating switch 12 is opened, two-way buffers 13 and 14 are operated as the two-way buffer, CPU21, ROM2, RAM3 and an external memory 11 are connected to common buses 5-7 and controlled by CPU21. In controlling of CPU1, the bus separating switch 12 is closed by the bus control part 15, and two-way buffers 13 and 14 prevent an output from the outside and CPU21 is separated.</p> |
