| 摘要 |
PURPOSE:To prevent malfunction due to difference in the length of wiring and the increase in the setup time by retarding a signal distributed to a slave flip- flop and passing the signal narrowering the pulse width through a differentiating circuit. CONSTITUTION:A clock signal from a clock input terminal 14 is fed to a master flip-flop 11 through gates 13, 13. Further, the clock signal is fed to the slave flip-flop 12 through the differentiating circuit 38 and the gates 13, 13. Thus, the clock fed to the flip-flop 12 is retarded by the number of gates including in the differentiation circuit 28. Since it is prevented that the flip-flops 11, 12 are logical 1 at the same time in this way, malfunction due to the difference in the wiring length and the increase in the setup time are prevented. |
