发明名称 DECODER CIRCUIT
摘要 <p>PURPOSE:To accelerate the discharge of a decoder circuit by discharging an electric charge, which is charged to an output in a writing or deletion mode, with the aid of a sufficiently low on-resistance. CONSTITUTION:In terms of this IGFETQ121, its drain and gate are connected to an output O' of a decoder circuit and to a signal DIS, respectively, and moreover a source and substrate are grounded. When a write or deletion mode is terminated, a pulse for becoming H for a certain period is impressed to the signal DIS. At this time, the electric charge, which is charged to a capacity added to the output O' in the write or deletion mode, is discharged to the ground by the prescribed time constant, while the voltage of the output O' comes to a power source voltage Vcc. The time width of the signal DIS can be set short when the on-resistance of the Q121 is made minimal. As a result, the discharging speed of the electric charge, which is charged to the capacity of the output O' in the write or deletion mode, is high. Then when the voltage of the output O' comes to the power source voltage Vcc, the operation becomes a read mode.</p>
申请公布号 JPS6150289(A) 申请公布日期 1986.03.12
申请号 JP19840171078 申请日期 1984.08.17
申请人 NEC CORP 发明人 HASHIMOTO KIYOKAZU
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
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