| 摘要 |
<p>PURPOSE:To eliminate the drop of the level of a decode line of a fixed memory by setting a control clock signal for a ROM line to L level before the decode line is discharged. CONSTITUTION:A node (c) of a latch circuit LA2 rises at a time t3 after a half period delay of a clock signal phi from a rise time t2 of an output phiDEC of an OR gate 25, and the output of an inverter 26 comes to L, while an output phiROM of a NAND gate 24 goes to H. Thus a node (a) of a shift register SL comes to L after one period delay, and a node (b) of a latch circuit LA1 goes to L by a half-period delay. Moreover after a half-period delay time t4 the node (c) comes to L, after which the output phiROM of the NAND gate 24 goes to L at a one- period delay time t5. Thus, since precharge is carried out at the timings phiROM and phiDEC after the potential of a ROM line is set to L level, the level of the decode line will not drop.</p> |
