Semiconductor integrated circuit device having a test circuit.

摘要

A semiconductor integrated circuit device having a test circuit including a plurality of gate cells (2) arranged in a matrix; wiring for connecting the gate cells so as to constitute a logic circuit; a plurality of row selection wires (3) provided along the gate cells in a row direction, each of the gate cells (2) being operatively connected to a row selection wire (3) a plurality of a column read-out wires (4) provided along the gate cells in a column direction, outputs of each of the gate cells (2) being operatively connected to column read-out wires (4), a row selection ring counter (6), operatively connected to the row selection wires (3), for selecting any of the row selection wires (3) and for the selecting of any of the gate cells (2) connected to the selected row selection wire (3); and a data selector (8) and ring counter (7) for reading out of the gate cells (2) arranged in the logic circuits through the column read-out wires (4).