发明名称 TIMER CIRCUIT
摘要 PURPOSE:To quicken the rise or fall of an output even to a long delay time by using an FET having a high input impedance so as to ulitize positive feedback. CONSTITUTION:When a switch 16 is closed, since a capacitor 14 is not charged and a gate potential of the FET7 is equal to a supplied voltage, and the internal impedance of the said FET7 is high by an electric field applied between the gate and source of the said FET7 in comparison with the said resistors 8 and 9. As time is elapsed, since the said capacitor 14 is charged through a resistor 15, the gate potential of the said FET7 is lower, and when it reaches a voltage to break down a Zener diode 10, the TR11 transits to the On state and the TR11 is turned on quickly through regeneration.
申请公布号 JPS6150419(A) 申请公布日期 1986.03.12
申请号 JP19840172967 申请日期 1984.08.20
申请人 ASOU TOKIE 发明人 ASO MAKOTO
分类号 H03K17/28;H03K17/284;(IPC1-7):H03K17/284 主分类号 H03K17/28
代理机构 代理人
主权项
地址