| 摘要 |
PURPOSE:To raise using efficiency of a memory bus and to stop the performance of respective CPU from falling by advancing a MMU request continuously from one CPU when a main memory unit request from plural CPU does not compete. CONSTITUTION:A MMU request CPU0-RQ inputted to a memory request control circuit is inputted to a latch 14, given to an AND gate 10 and sent to CPU. A priority cycle signal CPU0-PRIC of CPU is given through an OR gate 20 and a latch 15 to the AND gate 10. At such a time, a latch 16 to preserve a using condition of a bank is cleared and the output of the latch 16 is fed to the AND gate 10. The MMU request CPU0-RQ and CPU1-RQ outputted from CPU are successively outputted to MMU. |
