发明名称 |
Method of manufacturing a semiconductor device having narrow coplanar silicon electrodes |
摘要 |
A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.
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申请公布号 |
US4574468(A) |
申请公布日期 |
1986.03.11 |
申请号 |
US19840657631 |
申请日期 |
1984.10.04 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
SLOTBOOM, JAN W.;MAAS, HENRICUS G. R.;APPELS, JOHANNES A.;KLAASSEN, FRANCOIS M. |
分类号 |
H01L29/762;H01L21/033;H01L21/339;H01L27/10;H01L29/76;H01L29/772;(IPC1-7):H01L21/90 |
主分类号 |
H01L29/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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