| 摘要 |
PURPOSE:To eliminate the limitation of the highest operation speed at the operation speed of a synchronizing circuit, and to compose an interface circuit of different kinds of ICs by adding a common synchronizing signal and both channel signals to a plural-channel signal and performing time-division multiplexing operation. CONSTITUTION:Synchronizing signal and CH address signal insertion parts 1-4 of the time-division multiplexing system add the common synchronizing signal F and addresses 001, 010...100 indicating respective channels CH1-CH4 to the respective CHs and supply them to a multiplexing circuit 5, which multiplexes the inputs according to a clock from a clock generator 9. The data and clock are applied from this circuit 5 to a demultiplexing circuit 6 and demultiplexed into the CH1-CH4, so that a synchronous detecting and CH address signal detecting part 8 detects the CH2 which is outputted fourth. This detecting part 8 controls a switch part 7 and switches the output of the circuit 6 to normal channels CH1-CH4, so that the maximum operation speed is not limited to the operation speed of the synchronizing circuit. |
