| 摘要 |
A synchronizing circuit using a switchable bistable element for synchronizing an asymmetric signal with the clock of a data processing system. The occurrence of a balanced or metastable state in the switchable bistable synchronizing element which can slow up the data transfer rate is inhibited by applying an asymmetric injection signal thereto having a frequency, magnitude and asymmetry such that the maintenance of a balanced or metastable state in the synchronizing element is inhibited without interfering with the normal switching operation thereof.
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